Improving the reliability of on-chip L2 cache using redundancy

  title={Improving the reliability of on-chip L2 cache using redundancy},
  author={Koustav Bhattacharya and Soontae Kim and N. Ranganathan},
  journal={2007 25th International Conference on Computer Design},
The reliability of large on-chip L2 cache poses a significant challenge due to technology scaling trends. As the minimum feature size continues to decrease, the L2 caches become more vulnerable to multi-bit soft errors. Traditionally, L2 caches have been protected from multi-bit soft errors using techniques like using error detection/correction codes or employing physical interleaving of cache bit lines to convert multi-bit errors into single-bit errors. These methods, however, incur large… CONTINUE READING


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