Improving the WCET computation in the presence of a lockable instruction cache in multitasking real-time systems

@article{Aparicio2011ImprovingTW,
  title={Improving the WCET computation in the presence of a lockable instruction cache in multitasking real-time systems},
  author={Luis C. Aparicio and Juan Segarra and Clemente Rodr{\'i}guez Lafuente and V{\'i}ctor Vi{\~n}als},
  journal={Journal of Systems Architecture - Embedded Systems Design},
  year={2011},
  volume={57},
  pages={695-706}
}
In multitasking real-time systems it is required to compute the WCET of each task and also the effects of interferences between tasks in the worst case. This is very complex with variable latency hardware, such as instruction cache memories, or, to a lesser extent, the line buffers usually found in the fetch path of commercial processors. Some methods disable cache replacement so that it is easier to model the cache behavior. The difficulty in these cache-locking methods lies in obtaining a… CONTINUE READING
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