Improving the Security of Dual-Rail Circuits

@inproceedings{Sokolov2004ImprovingTS,
  title={Improving the Security of Dual-Rail Circuits},
  author={Danil Sokolov and Julian P. Murphy and Alexandre V. Bystrov and Alexandre Yakovlev},
  booktitle={CHES},
  year={2004}
}
Dual-rail encoding, return-to-spacer protocol and hazard-free logic can be used to resist differential power analysis attacks by making the power consumption independent of processed data. Standard dual-rail logic uses a protocol with a single spacer, e.g. all-zeroes, which gives rise to power balancing problems. We address these problems by incorporating two spacers; the spacers alternate between adjacent clock cycles. This guarantees that all gates switch in each clock cycle regardless of the… CONTINUE READING
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