Improving the ESD self-protection capability of integrated power NLDMOS arrays
@article{Vashchenko2010ImprovingTE, title={Improving the ESD self-protection capability of integrated power NLDMOS arrays}, author={Vladislav A. Vashchenko and Andy Strachan and Dimitri Linten and David LaFonteese and Ann Concannon and Mirko Scholz and Steven Thijs and Ph. Jansen and P. Hopper and Guido Groeseneken}, journal={Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2010}, year={2010}, pages={1-8} }
The self-protection capability (SPC) of integrated power arrays in ESD regimes has been studied for the case of integrated 100 V NLDMOS arrays in a BCD process. A new practical methodology for array comparison has been experimentally validated in order to take into account both gate coupling and avalanche current effects. Using TLP and electrical test methods, two orders of magnitude improvement of SPC has been demonstrated by implementation changes to array design. The effects of the Pbody…
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