An energy-efficient memory hierarchy for multi-issue processors
A limiting performance factor for soft cores that exploit high instruction-level parallelism (ILP) is the need of a high performance multiport memory to provide data at the rate it can be consumed by the available functional units. At the same time, FPGAs contain block RAMs (BRAMs) that provide enormous bandwidth, especially when data is spread through multiple blocks of independent address spaces. We present a novel technique to cope with the multiport memory problem and increase performance in very long instruction word (VLIW) FPGA-based soft-core processors. We emulate the use of a multi-ported memory system through the use of multiple single-ported memories, which are controlled at the software level. Experimental results demonstrate that our technique can improve performance on data-driven and control-driven applications where data reuse is found. Measurements show performance improvements of up to 2.15x for a Filter benchmark, a data-driven application, and 1.25x for a Knuth-Morris-Pratt (KMP) string search, a control-driven application. These improvements are achieved while maintaining the same area of the baseline soft processor core.