Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology

  title={Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology},
  author={Vojin G. Oklobdzija and David Villeger},
  journal={IEEE Trans. VLSI Syst.},
Absfract-In this paper we discuss improvements in bit reduction techniques in a parallel multiplier and the use of a final adder which is optimized for the uneven signal arrival profile. Different architectures of the column compressors and the use of carry propagate adders which take advantage of the speed of the carry signal are considered. The column compressors configuration is optimized in order to reduce the longest signal path. The final adder is designed for the uneven input arrival… CONTINUE READING
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A 4.1-nS CMOS S4 x 54 b multiplier using pass

  • San Francisco
  • 1993

Diplome d’Ingenieur in microelectronics from Ecole Superieure d’Ingenieurs en Electrotechnique (ESIEE), Paris, France, in July 1993 after a six-month project at the University of California, Davis

  • David Villeger
  • 1993

Multiplier design utilizing improved column compression tree and optimired final adder in CMOS technology,

  • G. Oklobdzija, D. Villeger
  • in Proc. 10th Anniv
  • 1993


  • Sept.
  • Bewick, “Fast multiplication: Algorithms and…
  • 1991

Computer Arithmetic, vols

  • E. E. Swartzlander
  • IEEE Comput. Soc. Press,
  • 1990

A self-timed multiplier with optimized final adder,

  • K. W. Yeung, R. K. Yu
  • LJniv. California,
  • 1989