Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology

@article{Oklobdzija1995ImprovingMD,
  title={Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology},
  author={Vojin G. Oklobdzija and David Villeger},
  journal={IEEE Trans. VLSI Syst.},
  year={1995},
  volume={3},
  pages={292-301}
}

• Vojin G. Oklobdzija, David Villeger
• Published in IEEE Trans. VLSI Syst. 1995
• DOI:10.1109/92.386228

Absfract-In this paper we discuss improvements in bit reduction techniques in a parallel multiplier and the use of a final adder which is optimized for the uneven signal arrival profile. Different architectures of the column compressors and the use of carry propagate adders which take advantage of the speed of the carry signal are considered. The column compressors configuration is optimized in order to reduce the longest signal path. The final adder is designed for the uneven input arrival… CONTINUE READING

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