Improving instruction-level parallelism by loop unrolling and dynamic memory disambiguation

@article{Davidson1995ImprovingIP,
  title={Improving instruction-level parallelism by loop unrolling and dynamic memory disambiguation},
  author={Jack W. Davidson and Sanjay Jinturkar},
  journal={Proceedings of the 28th Annual International Symposium on Microarchitecture},
  year={1995},
  pages={125-132}
}
Modulo scheduling is a well defined local scheduling based software pipelining technique. One disadvantage of traditional modulo scheduling is that it has a single initiation interval (II) for loops with multiple execution paths. Thus, shorter or more frequently executed paths will be penalized by longer or less frequently executed paths. Furthermore, for architectures with predicated execution, this single-II must be large enough to satisfy the resource and recurrence requirements of all… CONTINUE READING

Similar Papers

Citations

Publications citing this paper.
SHOWING 1-10 OF 25 CITATIONS

Software bubbles: using predication to compensate for aliasing in software pipelines

  • Proceedings.International Conference on Parallel Architectures and Compilation Techniques
  • 2002
VIEW 5 EXCERPTS
CITES BACKGROUND & METHODS
HIGHLY INFLUENCED

Exploiting Asymmetric SIMD Register Configurations in ARM-to-x86 Dynamic Binary Translation

  • 2017 26th International Conference on Parallel Architectures and Compilation Techniques (PACT)
  • 2017
VIEW 2 EXCERPTS
CITES BACKGROUND

HarvOS: Efficient Code Instrumentation for Transiently-Powered Embedded Sensing

  • 2017 16th ACM/IEEE International Conference on Information Processing in Sensor Networks (IPSN)
  • 2017
VIEW 1 EXCERPT
CITES METHODS

GROPHECY: GPU performance projection from CPU code skeletons

  • 2011 International Conference for High Performance Computing, Networking, Storage and Analysis (SC)
  • 2011
VIEW 1 EXCERPT
CITES BACKGROUND

Implementation of OpenVG Path and Paint Algorithms on Synchronous Data Triggered Architecture with Optimization

  • 2009 IEEE International Conference on Networking, Architecture, and Storage
  • 2009
VIEW 1 EXCERPT
CITES BACKGROUND

MPSoC memory optimization using program transformation

  • ACM Trans. Design Autom. Electr. Syst.
  • 2007
VIEW 2 EXCERPTS
CITES METHODS

A Measurement Study of the Linux TCP/IP Stack Performance and Scalability on SMP systems

  • 2006 1st International Conference on Communication Systems Software & Middleware
  • 2006
VIEW 1 EXCERPT
CITES METHODS

References

Publications referenced by this paper.
SHOWING 1-10 OF 17 REFERENCES

Dynamic memory disambiguation for array references

  • Proceedings of MICRO-27. The 27th Annual IEEE/ACM International Symposium on Microarchitecture
  • 1994
VIEW 8 EXCERPTS
HIGHLY INFLUENTIAL

Speculative disambiguation: a compilation technique for dynamic memory disambiguation

  • Proceedings of 21 International Symposium on Computer Architecture
  • 1994
VIEW 6 EXCERPTS
HIGHLY INFLUENTIAL

The Advantages of Machine-Dependent Global Optimization

  • Programming Languages and System Architectures
  • 1994
VIEW 10 EXCERPTS
HIGHLY INFLUENTIAL

Memory bandwidth optimizations for wide-bus machines

  • [1993] Proceedings of the Twenty-sixth Hawaii International Conference on System Sciences
  • 1993
VIEW 8 EXCERPTS
HIGHLY INFLUENTIAL

Improving Instructionlevel Parallelism by Loop Unrolling and Dynamic memory Disambiguation

J. W. Davidson, S. Jinturkar
  • Technical Report CS-95-13,
  • 1995
VIEW 6 EXCERPTS
HIGHLY INFLUENTIAL