Improving dual Vt technology by simultaneous gate sizing and mechanical stress optimization

@article{Gu2011ImprovingDV,
  title={Improving dual Vt technology by simultaneous gate sizing and mechanical stress optimization},
  author={Junjun Gu and Gang Qu and Lin Yuan and Cheng Zhuo},
  journal={2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)},
  year={2011},
  pages={732-735}
}
Process-induced mechanical stress is used to enhance carrier mobility and drive current in contemporary CMOS technologies. Stressed cells have reduced delay but larger leakage consumption. Its efficient power/delay trading ratio makes mechanical stress an enticing alternative to other power optimization techniques. This paper proposes an effective urgentpath guided approach that improves dual Vt technique by incorporating gate sizing and mechanical stress simultaneously. The introduction of… CONTINUE READING

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Key Quantitative Results

  • The introduction of mechanical stress is shown to achieve 9.8% leakage and 2.8% total power savings over combined gate sizing and dual Vt approach.

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Mechanical stress aware optimization for leakage power reduction

  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • 2010
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