Improving design verifiability by early RTL coverability analysis


Achieving high coverage is an important goal in design verification. Fixing coverability problems found at the verification stage, however, can require tremendous effort. To address this problem, we propose a flow for analyzing code and variable-toggle coverability at the early-RTL block-level stage. In addition, we devise a novel technique to analyze the… (More)
DOI: 10.1109/MEMCOD.2012.6292297


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