Improving Test Pattern Compactness in SAT-based ATPG

@article{Eggersgluss2007ImprovingTP,
  title={Improving Test Pattern Compactness in SAT-based ATPG},
  author={Stephan Eggersgluss and Rolf Drechsler},
  journal={16th Asian Test Symposium (ATS 2007)},
  year={2007},
  pages={445-452}
}
Automatic test pattern generation (ATPG) is one of the core problems in testing of digital circuits. ATPG algorithms based on Boolean Satisfiability (SAT) turned out to be very powerful, due to recent advances in SAT- based proof engines. SAT-based ATPG clearly outperforms classical approaches especially for hard-to-detect faults. But due to the SAT provers, a major drawback of the resulting test patterns is that a large number of input bits is specified. Thus, the resulting patterns are not… CONTINUE READING

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References

Publications referenced by this paper.
SHOWING 1-10 OF 19 REFERENCES

Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults

  • 2007 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2007)
  • 2007

Experimental Studies on SAT-Based ATPG for Gate Delay Faults

  • 37th International Symposium on Multiple-Valued Logic (ISMVL'07)
  • 2007

Efficiency of Multi-Valued Encoding in SAT-based ATPG

  • 36th International Symposium on Multiple-Valued Logic (ISMVL'06)
  • 2006
VIEW 1 EXCERPT

PASSAT: efficient SAT-based test pattern generation for industrial circuits

  • IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)
  • 2005
VIEW 1 EXCERPT

Managing don't cares in Boolean satisfiability

  • Proceedings Design, Automation and Test in Europe Conference and Exhibition
  • 2004
VIEW 1 EXCERPT

Chaff: engineering an efficient SAT solver

  • Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)
  • 2001
VIEW 1 EXCERPT