Improving Test Pattern Compactness in SAT-based ATPG

@article{Eggersgluss2007ImprovingTP,
  title={Improving Test Pattern Compactness in SAT-based ATPG},
  author={S. Eggersgluss and R. Drechsler},
  journal={16th Asian Test Symposium (ATS 2007)},
  year={2007},
  pages={445-452}
}
  • S. Eggersgluss, R. Drechsler
  • Published 2007
  • Computer Science
  • 16th Asian Test Symposium (ATS 2007)
  • Automatic test pattern generation (ATPG) is one of the core problems in testing of digital circuits. [...] Key Result SAT-based ATPG clearly outperforms classical approaches especially for hard-to-detect faults. But due to the SAT provers, a major drawback of the resulting test patterns is that a large number of input bits is specified. Thus, the resulting patterns are not well suited for test compaction and compression. In this paper we present techniques to increase the number of unspecified bits in test…Expand Abstract
    19 Citations
    Speeding up SAT-Based ATPG Using Dynamic Clause Activation
    • 13
    • PDF
    Improved SAT-based ATPG: More constraints, better compaction
    • 47
    • PDF
    SAT-Based Test Pattern Generation with Improved Dynamic Compaction
    • A. Czutro, S. Reddy, I. Polian, B. Becker
    • Mathematics, Computer Science
    • 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems
    • 2014
    • 8
    Efficient Data Structures and Methodologies for SAT-Based ATPG Providing High Fault Coverage in Industrial Application
    • 18
    Robust algorithms for high quality Test Pattern Generation using Boolean Satisfiability
    • 10
    • PDF
    Dynamic Compaction in SAT-Based ATPG
    • 26
    • Highly Influenced
    • PDF
    PASSAT 2.0: A multi-functional SAT-based testing framework
    • 6
    Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis
    • 46
    • PDF
    Efficiency and applications of SAT-based test pattern generation: complex fault models and optimisation problems
    • 1
    • Highly Influenced
    • PDF

    References

    SHOWING 1-10 OF 20 REFERENCES
    PASSAT: efficient SAT-based test pattern generation for industrial circuits
    • 51
    • PDF
    Efficiency of Multi-Valued Encoding in SAT-based ATPG
    • 22
    • PDF
    Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults
    • 11
    • PDF
    SAT-based ATPG for Path Delay Faults in Sequential Circuits
    • 11
    • PDF
    Combinational test generation using satisfiability
    • 341
    • PDF
    Test pattern generation using Boolean satisfiability
    • T. Larrabee
    • Computer Science
    • IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
    • 1992
    • 758
    • PDF
    IGRAINE-an Implication GRaph-bAsed engINE for fast implication, justification, and propagation
    • 57
    Minimal Assignments for Bounded Model Checking
    • 116
    • PDF
    An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
    • P. Goel
    • Computer Science
    • IEEE Transactions on Computers
    • 1981
    • 1,120
    • PDF
    Chaff: engineering an efficient SAT solver
    • 3,509
    • PDF