Improving SAT-Based Bounded Model Checking by Means of BDD-Based Approximate Traversals

Abstract

Binary Decision Diagrams (BDDs) have been widely used for hardware verification since the beginning of the ý90s, whereas Boolean Satisfiability (SAT) has been gaining ground more recently, with the introduction of Bounded Model Cheking (BMC). In this paper we dovetail BDD and SAT based methods to improve the efficiency of BMC. More specifically, we first… (More)
DOI: 10.3217/jucs-010-12-1693

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