Improving Bandwidth while Managing Phase Noise and Spurs in Fractional-N PLL

Abstract

The loop bandwidth of fractional-N PLL is a desirable parameter for many wireless communication applications. To improve bandwidth design tradeoffs must be made among different circuit blocks. The key to successful implementation of a wideband fractional-N synthesizer is in managing jitter and spurious performance. In this paper we compare several… (More)
DOI: 10.1109/ISVLSI.2008.47

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