Improving Bandwidth Utilization using Eager Writeback

  title={Improving Bandwidth Utilization using Eager Writeback},
  author={Hsien-Hsin S. Lee and Gary S. Tyson and Matthew K. Farrens},
  journal={J. Instruction-Level Parallelism},
Cache memories have been incorporated into almost all modern, general-purpose microprocessors. To maintain data consistency between cache structures and the rest of the memory systems, most of these caches employ either a writeback or a write-through strategy to deal with store operations. Writethrough caches propagate data to more distant memory levels at the time each store occurs, producing a significant bus traffic overhead to maintain consistency between the memory hierarchy levels… CONTINUE READING