Improvement of 48 nm TANOS NAND Cell Performance by Introduction of a Removable Encapsulation Liner

@article{Beug2009ImprovementO4,
  title={Improvement of 48 nm TANOS NAND Cell Performance by Introduction of a Removable Encapsulation Liner},
  author={M. Florian Beug and Thomas Melde and J. Paul and U. Bewersdorff-Sarlette and M. Czernohorsky and V. Beyer and R. Hoffmann and Klaus Seidel and D. A. Lohr and Lennart Bach and Roman Knoefler and Armin Tilke},
  journal={2009 IEEE International Memory Workshop},
  year={2009},
  pages={1-2}
}
Introduction: Charge trapping (CT) memory cells are a promising candidate to replace floating gate (FG) cells in NAND applications around the 30 nm technology node [1]. Difficulties to place the control gate (CG) plug in between adjacent FG cells cause serious problems to provide a sufficiently high gate coupling ratio. As a result the program and erase… CONTINUE READING