Improved single-stage kickback-rejected comparator for high speed and low noise flash ADCs

Abstract

In this paper, the conventional single-stage latched comparator is improved for both high speed and low noise flash ADCs. In the proposed method for high-speed applications, the common mode level of output voltage is preserved unchanged during both amplification and latch operations, to speed up the comparison of small voltage differences. Also, the… (More)

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Cite this paper

@article{Kazeminia2013ImprovedSK, title={Improved single-stage kickback-rejected comparator for high speed and low noise flash ADCs}, author={Sarang Kazeminia and Obalit Shino and Ehsan Haghighi and Khayrollah Hadidi}, journal={2013 European Conference on Circuit Theory and Design (ECCTD)}, year={2013}, pages={1-4} }