Improved RNS FIR filter architectures

  title={Improved RNS FIR filter architectures},
  author={Richard Conway and John S. Nelson},
  journal={IEEE Transactions on Circuits and Systems II: Express Briefs},
A new architecture for implementing finite-impulse response (FIR) filters using the residue number system (RNS) is detailed. The design is based on using a restricted modulus set, with moduli of the form 2/sup n/,2/sup n/-1, and 2/sup n/+1. This does not restrict the modulus set to the common 3 modulus set {2/sup n/-1,2/sup n/,2/sup n/+1}, but any number of pairwise relatively prime moduli of this form, for example, {5,7,17,31,32,33}. Based on a comparison with a 2's complement design, the new… CONTINUE READING
Highly Cited
This paper has 312 citations. REVIEW CITATIONS


Publications citing this paper.
Showing 1-10 of 93 extracted citations

Data Conversion in Residue Number System

View 7 Excerpts
Method Support
Highly Influenced

Hierarchical residue number systems with small moduli and simple converters

Applied Mathematics and Computer Science • 2011
View 4 Excerpts
Method Support
Highly Influenced

FIR Filter Realization via Deferred End-Around Carry Modular Addition

IEEE Transactions on Circuits and Systems I: Regular Papers • 2018
View 1 Excerpt

313 Citations

Citations per Year
Semantic Scholar estimates that this publication has 313 citations based on the available data.

See our FAQ for additional information.


Publications referenced by this paper.
Showing 1-10 of 10 references

A New Modulo 2a + 1 Multiplier

View 5 Excerpts
Highly Influenced

Residue Number Systems: Algorithms and Architectures

A. Mohan
New York: Kluwer, • 2002
View 1 Excerpt

New RNS architectures for digital signal processing

R. Conway
Ph.D. dissertation, Univ. of Limerick, Limerick, Ireland, Sept. 2001. • 2001
View 2 Excerpts

Modulo 2 1 arithmetic hardware algorithm using signed-digit representation

S. Wei, K. Shimizu
IEICE Trans. Inform. Syst., vol. E79-D, no. 3, pp. 242–246, Mar. 1996. • 1996
View 1 Excerpt

A note on free accumulation in VLSI filter architectures

P. R. Cappello, K. Steiglitz
IEEE Trans. Circuits Syst., vol. CAS-32, pp. 291–296, Mar. 1985. • 1985
View 1 Excerpt

Merged arithmetic for signal processing

1978 IEEE 4th Symposium onomputer Arithmetic (ARITH) • 1978
View 1 Excerpt