Improved Fault Tolerant SRAM Cell Design & Layout in 130nm Technology
@inproceedings{Radhakrishnan2014ImprovedFT,
title={Improved Fault Tolerant SRAM Cell Design & Layout in 130nm Technology},
author={Govindakrishnan Radhakrishnan},
year={2014}
}..................................................................................................iii TABLE OF CONTENTS....................................................................................iv LIST OF FIGURES.........................................................................................vii LIST OF TABLES...........................................................................................xi ABBREVIATIONS… CONTINUE READING
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One Citation
References
SHOWING 1-10 OF 36 REFERENCES
Investigation of multi-bit upsets in a 150 nm technology SRAM device
- Computer Science
- IEEE Transactions on Nuclear Science
- 2005
- 188
CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test
- Computer Science, Engineering
- 2008
- 222
- PDF
A Soft Error Tolerant 10T SRAM Bit-Cell With Differential Read Capability
- Physics
- IEEE Transactions on Nuclear Science
- 2009
- 157
- PDF
Analysis of radiation-hardening techniques for 6T SRAMs with structured layouts
- Engineering
- 2009 IEEE International Reliability Physics Symposium
- 2009
- 9
Single-Event Upsets and Multiple-Bit Upsets on a 45 nm SOI SRAM
- Engineering
- IEEE Transactions on Nuclear Science
- 2009
- 144
- Highly Influential
LEAP: Layout Design through Error-Aware Transistor Positioning for soft-error resilient sequential cell design
- Engineering
- 2010 IEEE International Reliability Physics Symposium
- 2010
- 121
Soft errors in advanced computer systems
- Engineering, Computer Science
- IEEE Design & Test of Computers
- 2005
- 774
- Highly Influential
- PDF