Implication-Based Gate-level Synthesis for Low-Power Topics: Technology-Independent, Combinational Logic Synthesis and Optimization

  • Published 1995

Abstract

The paper presents a new logic optimization method of multi-level combinational CMOS circuits, which minimizes area and power. Present methods to reduce power on logic circuits apply functional methods like logic factorization on the Boolean networks. The method described here uses Boolean transformations that exploit implications at the gate-level based on… (More)

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Cite this paper

@inproceedings{1995ImplicationBasedGS, title={Implication-Based Gate-level Synthesis for Low-Power Topics: Technology-Independent, Combinational Logic Synthesis and Optimization}, author={}, year={1995} }