Implementation of testable reversible sequential circuit on FPGA

Abstract

The design of testable sequential circuits by two vectors using conservative logic. The proposed sequential circuits based on conservative logic outclass the traditional sequential circuits built using classical gates in terms of testability. Any sequential circuits based on conservative logic can test for stuck-at 0 and stuck-at 1 fault by using two… (More)

Topics

1 Figure or Table

Cite this paper

@article{Prasanna2015ImplementationOT, title={Implementation of testable reversible sequential circuit on FPGA}, author={M. Prasanna and S. Amudha}, journal={2015 International Conference on Innovations in Information, Embedded and Communication Systems (ICIIECS)}, year={2015}, pages={1-5} }