Implementation of heart rate variability signal processing into FPGA: System on-chip design

Abstract

In this paper, we try to develop and implement the HRV signal processing into a Field Programmable Gate Array (FPGA) for extracting this signals feature. The hardware implementing algorithm was developed in Verilog Hardware Description Language (HDL). In designed hardware, after defining the number of samples in the input, it extracts and analyses the time… (More)

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Cite this paper

@article{Rezaei2013ImplementationOH, title={Implementation of heart rate variability signal processing into FPGA: System on-chip design}, author={Shahab Rezaei and Sadaf Moharreri and Hossein Ajorloo and Siamak Salavatian}, journal={Computing in Cardiology 2013}, year={2013}, pages={397-400} }