Corpus ID: 212581302

Implementation of an Efficient Multiplier based on Vedic Mathematics Using EDA Tool

@inproceedings{Verma2012ImplementationOA,
  title={Implementation of an Efficient Multiplier based on Vedic Mathematics Using EDA Tool},
  author={P. Verma and K. K. Mehta},
  year={2012}
}
  • P. Verma, K. K. Mehta
  • Published 2012
  • A high speed processor depends greatly on the multiplier as it is one of the key hardware blocks in most digital signal processing systems as well as in general processors. This paper presents a high speed 8x8 bit Vedic multiplier architecture which is quite different from the Conventional method of multiplication like add and shift. The most significant aspect of the proposed method is that, the developed multiplier architecture is based on Vertical and Crosswise structure of Ancient Indian… CONTINUE READING
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    References

    SHOWING 1-10 OF 17 REFERENCES
    A Time-Area-Power Efficient Multiplier and Square Architecture Based on Ancient Indian Vedic Mathematics
    • 81
    • PDF
    High speed energy efficient ALU design using Vedic multiplication techniques
    • 164
    Conventional versus Vedic Mathematical Method for Hardware Implementation of a Multiplier
    • 140