# Implementation of an Efficient Multiplier based on Vedic Mathematics Using EDA Tool

@inproceedings{Verma2012ImplementationOA, title={Implementation of an Efficient Multiplier based on Vedic Mathematics Using EDA Tool}, author={P. Verma and K. K. Mehta}, year={2012} }

A high speed processor depends greatly on the multiplier as it is one of the key hardware blocks in most digital signal processing systems as well as in general processors. This paper presents a high speed 8x8 bit Vedic multiplier architecture which is quite different from the Conventional method of multiplication like add and shift. The most significant aspect of the proposed method is that, the developed multiplier architecture is based on Vertical and Crosswise structure of Ancient Indian…

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## 64 Citations

### Implementation of an Efficient Multiplier based on Vedic Mathematics Using High speed adder

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The proposed high speed Vedic multiplier architecture uses Carry look ahead adder as a key block for fast addition and the performance of multiplier is vastly improved and complexity gets reduced for inputs of larger no of bits.

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The work has proved the efficiency of Urdhva tiryakbhyam – Vedic method for multiplication which strikes a difference in the actual process of multiplication itself and enables parallel generation of intermediate products, eliminates unwanted multiplication steps with zeros and scaled to higher bit levels.

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The proposed method is efficient and fast, wherein the processing involves the vertical and crossed multiplication of precedent Vedic mathematics and incorporates the partial products followed by additive result that too in a single step.

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Study on high speed 8x8 bit Vedic multiplier architecture which is quite different from the Conventional method of multiplication like add and shift is presented.

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The proposed Urdhva and Nikhilam multipliers achieve 60, 77, and 37%, 50% improvement in speed and power respectively, as compared with the power consumption of the conventional array multipliers.

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The proposed architecture is for two 8-bit numbers, the multiplier and multiplicand each arc grouped as 4- bit numbers; so that it decomposes into 4x4 multiplication modules, which gives chance for modular design where smaller blocks can be used to design the bigger one.

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This paper proposed an 8-bit multiplier using the new methodology of Vedic Mathematics called as Urdhva-Tiryagbhyam sutra which is used for generating the partial products in Vedic multiplier and depicted the design of an efficient 8×8 binary arithmetic multiplier by using Vedic mathematics.

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BACKGROUND This paper proposes the design of high speed Vedic multiplier using the techniques of Vedic Mathematics that have been modified to improve performance. A high-speed processor depends…

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