Implementation of an 8-Core, 64-Thread, Power-Efficient SPARC Server on a Chip

@article{Nawathe2008ImplementationOA,
  title={Implementation of an 8-Core, 64-Thread, Power-Efficient SPARC Server on a Chip},
  author={U. G. Nawathe and M. Hassan and K. C. Yen and A. Kumar and A. Ramachandran and D. Greenhill},
  journal={IEEE Journal of Solid-State Circuits},
  year={2008},
  volume={43},
  pages={6-20}
}
  • U.G. Nawathe, M. Hassan, +3 authors D. Greenhill
  • Published 2008
  • Computer Science
  • IEEE Journal of Solid-State Circuits
    • The second in the Niagara series of processors (Niagara2) from Sun Microsystems is based on the power-efficient chip multi-threading (CMT) architecture optimized for Space, Watts (Power), and Performance (SWaP) [SWap Rating = Performance/(Space * Power) ]. It doubles the throughput performance and performance/watt, and provides >10times improvement in floating point throughput performance as compared to UltraSPARC T1 (Niagara1). There are two 10 Gb Ethernet ports on chip. Niagara2 has eight… CONTINUE READING
    View on IEEE
    ee.unlv.edu
    93 Citations
    Highly Influential Citations
    7
    Background Citations
    36
    Methods Citations
    27
    93 Citations
    Citation Type

    Citation Type

    A 40 nm 16-Core 128-Thread SPARC SoC Processor
    • 61
    A 3.6 GHz 16-Core SPARC SoC Processor in 28 nm
    • 17
    Throughput-Oriented Multicore Processors
    • 2
    • Highly Influenced
    CHOMP: A Framework and Instruction Set for Latency Tolerant, Massively Multithreaded Processors
    • 10
    Scalable cores in chip multiprocessors
    • 1
    • PDF
    FPGA Prototyping of Manycore Multinode Systems for Irregular Applications
    • PDF
    Rx Stack Accelerator for 10 GbE Integrated NIC
    • 4
    • PDF
    McPAT 1 . 0 : An Integrated Power , Area , and Timing Modeling Framework for Multicore Architectures ∗
    • 37
    • Highly Influenced
    • PDF
    Composable Multicore Chips
    Dynamic voltage and frequency scaling with multi-clock distribution systems on SPARC core

    References

    SHOWING 1-10 OF 13 REFERENCES
    An 8-Core 64-Thread 64b Power-Efficient SPARC SoC
    • 119
    Niagara-2: A highly threaded server-on-a-chip
    • Greg Grohoski
    • Computer Science
    • 2006 IEEE Hot Chips 18 Symposium (HCS)
    • 2006
    • 65
    A Single-Cycle-Access 128-Entry Fully Associative TLB for Multi-Core Multi-Threaded Server-on-a-Chip
    • 3
    Implementation of a fourth-generation 1.8-GHz dual-core SPARC V9 microprocessor
    • 22
    Implementation of a 4/sup th/-generation 1.8GHz dual-core SPARC V9 microprocessor
    • J. Hart, Swee Yew Choe, +6 authors J. Wu
    • Computer Science
    • ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005.
    • 2005
    • 40
    A low-jitter 1.9-V CMOS PLL for UltraSPARC microprocessor applications
    • 64
    2/3 divider cell using phase switching technique
    • 4
    Phase mismatch in phase switching frequency dividers
    • M. El sheikh, A. Hafez
    • Materials Science
    • Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)
    • 2003
    • 4
    A Power-Efficient High-Throughput 32-Thread SPARC Processor
    • 76
    Niagara2: A highly threaded server-on-a-chip, " presented at the 18th Hot Chips Symp
    • Niagara2: A highly threaded server-on-a-chip, " presented at the 18th Hot Chips Symp
    • 2006