Implementation of an 8-Core, 64-Thread, Power-Efficient SPARC Server on a Chip

@article{Nawathe2008ImplementationOA,
  title={Implementation of an 8-Core, 64-Thread, Power-Efficient SPARC Server on a Chip},
  author={U. G. Nawathe and M. Hassan and K. C. Yen and A. Kumar and A. Ramachandran and D. Greenhill},
  journal={IEEE Journal of Solid-State Circuits},
  year={2008},
  volume={43},
  pages={6-20}
}
  • U.G. Nawathe, M. Hassan, +3 authors D. Greenhill
  • Published 2008
  • Computer Science
  • IEEE Journal of Solid-State Circuits
  • The second in the Niagara series of processors (Niagara2) from Sun Microsystems is based on the power-efficient chip multi-threading (CMT) architecture optimized for Space, Watts (Power), and Performance (SWaP) [SWap Rating = Performance/(Space * Power) ]. It doubles the throughput performance and performance/watt, and provides >10times improvement in floating point throughput performance as compared to UltraSPARC T1 (Niagara1). There are two 10 Gb Ethernet ports on chip. Niagara2 has eight… CONTINUE READING
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