Implementation of a Transaction Level Assertion Framework in SystemC

  title={Implementation of a Transaction Level Assertion Framework in SystemC},
  author={Wolfgang Ecker and Volkan Esen and Thomas Steininger and Michael Velten and Michael Hull},
  journal={2007 Design, Automation & Test in Europe Conference & Exhibition},
Current hardware design and verification methodologies reflect a trend towards abstraction levels higher than RTL, referred to as transaction level (TL). Since transaction level models (TLMs) are used for early prototyping and as reference models for the verification of their RTL representation, the quality assurance of TLMs is vital. Assertion based verification (ABV) of RTL models has improved quality assurance of IP blocks and SoC systems to a great extent. Since mapping of an RTL ABV… CONTINUE READING
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