Corpus ID: 14940475

Implementation of a Single FFT Processor

@inproceedings{Hampson2002ImplementationOA,
  title={Implementation of a Single FFT Processor},
  author={Grant A. Hampson},
  year={2002}
}
This document describes a FPGA implementation and simulation of the FFT component of the IIP Radiometer RFI processor described in [1]. A possible implementation of this FFT component has been previously described in [2]. Here a single FFT processor will be implemented and tested before proceeding to a larger design consisting of many such processors. This document is broken into three separate sections. The first section presents simulations of the Altera FFT Megacore, with special emphasis on… Expand
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This document describes a FPGA implementation and simulation of the FFT component of the IIP Radiometer RFI processor described in [1]. The FFT processor will ideally be capable of processing 100% ofExpand
A 256 k @ 32-bit Capture Card for the IIP Radiometer
The digital part of the radiometer project is broken into several stages of development (Digital IF, APB, FFT, etc) and it is important to be able to capture results from each stage. It is of equalExpand
On-Air Test of the IIP Receiver Using Observations of an ATC Radar
TLDR
A quick sanity check of the IIP radiometer hardware developed to date is documents, using observations of a nearby 1331 MHz air traffic control (ATC) radar, which confirms that the dynamic range of the receiver is greater than 40 dB. Expand
Implementation of the Asynchronous Pulse Blanker
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X0X" => B"010", B"00010011"; --start FFT B"010
  • X0X" => B"010", B"00010011"; --start FFT B"010
  • 1100