- Published 1992

Systolic arrays belong to the class of pipelined array architectures where many identical processing elements (PE ́s) are interconnected locally so that data can be passed from all PE ́s to their respective neighbors synchronously and in parallel. In principle, all of them perform the same basic operation on their current operands in one clock cycle. At the University of Mannheim a systolic processor array is under development specialized to a specific pattern recognition task that has extreme high-speed requirements. The system is a systolic processor for the identification of circular particle tracks in a 2D projection. For each well defined track, the starting angle and the radius of curvature is computed in less than 5 μs. The system consists of a Hough transform processor that determines well defined tracks, and an Euler processor that counts their number by applying the Euler relation to the thresholded result of the Hough transform. A systolic processor consisting of 35×32 processing elements is being implemented in programmable gate arrays. It is scalable, so that the processor can easily be adapted to different generalized Hough transforms. The data and control flow in the systolic processor have been simulated completely.

@inproceedings{Conen1992ImplementationOA,
title={Implementation of a Parallel Hough Transform Processor},
author={Wolfram Conen and Frank Klefenz and Reinhard M{\"a}nner and Ralf Zoz},
year={1992}
}