Implementation of a Floating-point Divider

In this paper, we present the VLSI implementation of a low power floating-point divider in CMOS 0.18μm technology using radix-2 over redundant number system. This divider implementation is well suited for IEEE 754 floating point standard and can be widely used in DSP applications. In the proposed divider designs, different PPM adders, based on 24, 22 and… CONTINUE READING