Implementation of a FFT radix 2 butterfly using serial RSFQ multiplier-adders

@article{Mukhanov1995ImplementationOA,
  title={Implementation of a FFT radix 2 butterfly using serial RSFQ multiplier-adders},
  author={O. A. Mukhanov and A. E. Kirichenko},
  journal={IEEE Transactions on Applied Superconductivity},
  year={1995},
  volume={5},
  pages={2461-2464}
}
We have designed a Decimation-in-Time (DIT) radix 2 butterfly integrated circuit. This circuit will be used to implement the 32-point Fast Fourier Transform (FFT) in a parallel data flow architecture. The radix 2 butterfly circuit uses serial RSFQ math and consists of four single bit-wide serial multipliers and eight carry-save serial adders. The circuit with 16-bit word-length employs only 3400 junctions, occupies an area of 3.8/spl times/2.0 mm/sup 2/, and dissipates less than 1.1 mW power… CONTINUE READING