Implementation of a 4 × 4-bit Multiplier in a Two Phase Drive Adiabatic Dynamic CMOS Logic

@inproceedings{Takahashi2007ImplementationOA,
  title={Implementation of a 4 × 4-bit Multiplier in a Two Phase Drive Adiabatic Dynamic CMOS Logic},
  author={Yasuhiro Takahashi and Toshikazu Sekine and Michio Yokoyama},
  year={2007}
}
An adiabatic logic is a technique to design low power digital VLSI’s. This paper describes the design and VLSI implementation of a multiplier using a two phase drive adiabatic dynamic CMOS logic (2PADCL) circuit. Circuit operation and performance have been evaluated using a 4×4-bit 2PADCL multiplier fabricated in a 1.2 μm CMOS process. The experimental results show that the multiplier was operated with clock frequencies 800 kHz. The total power dissipation of the 4 × 4-bit 2PADCL multiplier was… CONTINUE READING
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