Implementation of Pseudo-Noise Sequence Generator on FPGA Using Verilog

Abstract

The objective of this paper is to develop a Pseudo-noise sequence generator implementation on FPGA using verilog HDL (hardware description language). Each functional module of this sequence gnerator is designed as a separate module and is tested for functionality by using ModelSim simulator of mentor graphics. FPGA implementation of Pseudo-noise sequence… (More)

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