Corpus ID: 212523176

Implementation of Multiplier using Vedic Algorithm

@inproceedings{Patil2013ImplementationOM,
  title={Implementation of Multiplier using Vedic Algorithm},
  author={Shivaraj Patil},
  year={2013}
}
  • Shivaraj Patil
  • Published 2013
  • 219  Abstract :Vedic mathematics is the name given to the ancient Indian system of mathematics that was rediscovered in the early twentieth century from ancient Indian sculptures (Vedas). This paper proposes the design of high speed Vedic Multiplier using the techniques of Vedic Mathematics that have been modified to improve performance. A high speed processor depends greatly on the multiplier as it is one of the key hardware blocks in most digital signal processing systems as well as in… CONTINUE READING
    71 Citations

    Figures and Tables from this paper

    Design and analysis of ALU: Vedic mathematics approach
    • 13
    Area efficient modified vedic multiplier
    • 22

    References

    SHOWING 1-10 OF 14 REFERENCES
    Multiplier design based on ancient Indian Vedic Mathematics
    • 202
    A Time-Area-Power Efficient Multiplier and Square Architecture Based on Ancient Indian Vedic Mathematics
    • 81
    • PDF
    Conventional versus Vedic Mathematical Method for Hardware Implementation of a Multiplier
    • 140
    The Implementation of Vedic Algorithms in Digital Signal Processing*
    • 85
    • PDF
    High speed energy efficient ALU design using Vedic multiplication techniques
    • 164
    Computer system architecture
    • 290