# Implementation of Multiplier using Vedic Algorithm

@inproceedings{Patil2013ImplementationOM, title={Implementation of Multiplier using Vedic Algorithm}, author={S. Patil}, year={2013} }

219 Abstract :Vedic mathematics is the name given to the ancient Indian system of mathematics that was rediscovered in the early twentieth century from ancient Indian sculptures (Vedas). This paper proposes the design of high speed Vedic Multiplier using the techniques of Vedic Mathematics that have been modified to improve performance. A high speed processor depends greatly on the multiplier as it is one of the key hardware blocks in most digital signal processing systems as well as in…

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## 89 Citations

### Design of 8 Bit Vedic Multiplier Using VHDL

- Computer Science
- 2014

The work has proved the efficiency of Urdhva tiryakbhyam – Vedic method for multiplication which strikes a difference in the actual process of multiplication itself and enables parallel generation of intermediate products, eliminates unwanted multiplication steps with zeros and scaled to higher bit levels.

### STRUCTURAL ANALYSIS OF VEDIC MULTIPLIER USING URDHVA-TIRYAKBHYAM SUTRA ALGORITHM FOR FPGA

- Computer Science
- 2017

BACKGROUND This paper proposes the design of high speed Vedic multiplier using the techniques of Vedic Mathematics that have been modified to improve performance. A high-speed processor depends…

### Design of 8 Bit Vedic Multiplier for Real & Complex Numbers Using VHDL Mr .

- Computer Science
- 2014

The work has proved the efficiency of Urdhva tiryakbhyam – Vedic method for multiplication which strikes a difference in the actual process of multiplication itself and enables parallel generation of intermediate products, eliminates unwanted multiplication steps with zeros and scaled to higher bit levels.

### High Speed Vedic Multiplier Design using FPGA

- Mathematics
- 2018

The proposed Vedic multiplier is based on the “Urdhava Triyagbhayam” sutra (algorithm), which has been traditionally used for the multiplication of two numbers in the decimal number system.

### Bit wise and delay of vedic multiplier

- Computer Science, Mathematics
- 2017

This paper wants to show the delay and utilization of components available for the multiplier by executing the code and the whole process was done in XILINX software.

### VLSI Implementation of Vedic Multiplier Using Urdhva – Tiryakbhyam Sutra in VHDL Environment : A Novelty

- Computer Science, Mathematics
- 2015

This paper proposed an 8-bit multiplier using the new methodology of Vedic Mathematics called as Urdhva-Tiryagbhyam sutra which is used for generating the partial products in Vedic multiplier and depicted the design of an efficient 8×8 binary arithmetic multiplier by using Vedic mathematics.

### Design and analysis of ALU: Vedic mathematics approach

- Computer ScienceInternational Conference on Computing, Communication & Automation
- 2015

The proposed method is efficient and fast, wherein the processing involves the vertical and crossed multiplication of precedent Vedic mathematics and incorporates the partial products followed by additive result that too in a single step.

### FPGA Implementation of Low Power and High Speed Vedic Multiplier using Vedic Mathematics

- Computer Science, Mathematics
- 2013

The proposed architecture is for two 8-bit numbers, the multiplier and multiplicand each arc grouped as 4- bit numbers; so that it decomposes into 4x4 multiplication modules, which gives chance for modular design where smaller blocks can be used to design the bigger one.

### Design and Implementation of Floating-point Vedic multiplier

- Computer Science
- 2020

VEDIC Mathematics is mathematical detail of 'Sixteen Simple Mathematical formula from the Vedas' as release by Sri Bharati Krishna Tirtha and the implementation of the Floating-point multiplier is done by using Vedic multiplication methods.

### Area efficient modified vedic multiplier

- Computer Science2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT)
- 2016

The efficiency of Urdhva Tiryagbhyam (vertical and crosswise) Vedic method for multiplication which is different from the process of normal multiplication is presented and is the most efficient algorithm that gives minimum delay for multiplication for all types of numbers irrespective of their size.

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This paper presents a high speed 8x8 bit Vedic multiplier architecture which is quite different from the Conventional method of multiplication like add and shift and is based on Vertical and Crosswise structure of Ancient Indian Vedic Mathematics.

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Vedic mathematics is the name given to the ancient Indian system of mathematics that was rediscovered in the early twentieth century from ancient Indian sculptures (Vedas). It mainly deals with Vedic…

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In FPGA implementation it has been found that the proposed Vedic multiplier and square are faster than array multiplier and Booth multiplier.

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Aim of this paper is to compare and prove implementation of normal multiplication and Vedic multiplication (using Urdhva Tiryakbhyam Sutra) on digital hardware requires same number of multiplication…

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Vedic mathematics is the name given to the ancient system of mathematics, or, to be precise, a unique technique of calculations based on simple rules and principles with which any mathematical…

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The efficiency of Urdhva Triyagbhyam-Vedic method for multiplication is proved which strikes a difference in the actual process of multiplication itself, which enables parallel generation of intermediate products, eliminates unwanted multiplication steps with zeros and scaled to higher bit levels using Karatsuba algorithm.

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It has been demonstrated that implementing the array and booth multiplier as 4x4 modules in the proposed architecture leads to a considerable improvement in their efficiency.

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