Implementation of High Speed FIR Filter using Serial and Parallel Distributed Arithmetic Algorithm

  title={Implementation of High Speed FIR Filter using Serial and Parallel Distributed Arithmetic Algorithm},
  author={S. Narendra and Pal Singh Harjit and Rakesh Kumar Sarin and Singh Sarabjeet},
  journal={International Journal of Computer Applications},
This paper describes the implementation of highly efficient multiplierless serial and parallel distributed arithmetic algorithm for FIR filters. Distributed Arithmetic (DA) had been used to implement a bit-serial scheme of a general symmetric version of an FIR filter due to its high stability and linearity by taking optimal advantage of the look-up table (LUT) based structure of FPGAs. The performance of the bitserial and bit-parallel DA technique for FIR filter design is analyzed and the… Expand
An Efficient Modified Distributed Arithmetic Architecture Suitable for FIR Filter
  • Narendiran S., J. P.
  • 2021 Sixth International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET)
  • 2021
One of the essential components of a Digital Signal Processing (DSP) system is the Finite Impulse Response (FIR) filter. FIR filter uses the Multiply and Accumulate (MAC) operation for itsExpand
Enhanced LUT for Modified Distributed Arithematic Architecture - FIR Filter
This paper presents Enhanced LUT for Modified Distributed Arithmetic Architecture for efficient implementation of finite impulse response (FIR) filter. This technique consists of shift registers,Expand
High Speed and Multiplierless Implementation of Half-Band Filter
Half-band FIR filters utilize less hardware compared to normal FIR filters. The efficiency of half-band filters derives from the fact that about half of the filter coefficients are zero, thus,Expand
Distributed Arithmetic Based Hybrid Architecture for Multiple Transforms
A Distributed Arithmetic (DA) based multitransform architecture for supporting 1-D 8-point DCT, DFT, DST and DWT is proposed and a multiplier-less architecture leading to reduced hardware is implemented in 45 nm CMOS technology in Cadence RTL compiler as well as on FPGA using Xilinx ISE. Expand
An approach to LUT based multiplier for short word length DSP systems
  • T. Memon, A. Pathan
  • Computer Science
  • 2018 International Conference on Signals and Systems (ICSigSys)
  • 2018
A way to use the Look-up tables to design three bit (3×3) constant coefficient unsigned integral multiplier for Short Word Length DSP systems is presented. Expand
Hardware Approach to Demodulate Satellite Relayed Video Signals
The Finite Impulse Response is utilized for satellite video signal demodulation because of one of a kind properties and the utilization of limited exactness and coefficients to speak to signals forExpand
A Review: FPGA Implementation of Reconfigurable Digital FIR Filter
This brief presents, the different methods namely conversion based approaches and memory based methods for implementation of FIR filter. It also presents an efficient implementation of Finite ImpulseExpand
An Efficient Low Power and High Speed Distributed Arithmetic Design for FIR Filter
This research work presents a low power and high speed efficient buffer based Distributed Algorithms and it is analyzed with Electro Cardio Gram (ECG) signal Finite Impulse Response (FIR) filter design to achieve better performance. Expand
Energy and discipline effective Implementation for Parallel FIR Filters utilizing FFAs and DA
This paper describes the implementation of two parallel FIR filter based on traditional method costs considerable hardware power and area . The Finite Impulse Response (FIR) filters mainly containExpand
Modified artificial bee colony optimisation based FIR filter design with experimental validation using field-programmable gate array
Two modified versions of a recently developed evolutionary technique i.e. artificial bee colony (ABC) algorithm for design of FIR filters are proposed and are found to outperform other non-convex algorithms in achieving the desired specifications. Expand


Algorithm Proposed For FIR Filter Cofficent Representation
  • International Journel of Mahematics and computer Sciences
  • 2008
An Algorithm Proposed for FIR Filter Coefficients Representation
This paper presents an algorithm proposed for modifying values and the number of non-zero coefficients used to represent the FIR digital pulse shaping filter response that will reduce the arithmetic complexity needed through the minimization of the non- zero values coefficients to get the filter output. Expand
HDL A guide to Digital Design and Synthesis”Second
  • 2007
Palnitkar,”Verilog HDL A guide to Digital Design and Synthesis”Second Edition-2007
  • Index Terms Computer Science
  • 2007
” Design of Digital FIR Filter Based on DDA algorithm ”
  • Journal of Applied Science
  • 2007
Hardware-efficient distributed arithmetic architecture for high-order digital filters
  • H. Yoo, David V. Anderson
  • Computer Science
  • Proceedings. (ICASSP '05). IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005.
  • 2005
FPGA implementation results confirm that the proposed DA architecture can implement a 1024-tap FIR filter with significantly smaller area usage than the original LUT-based DA and the Lut-less DA-OBC. Expand
A high-speed FIR digital filter with CSD coefficients implemented on FPGA
A very fast and low-complexity FIR digital filter on FPGA is presented, whose coefficients are expressed as canonic signed digit (CSD) code are realized with wired-shifters, adders and subtracters. Expand
Efficient design of application specific DSP cores using FPGAs
The results show that PDA designs with a digit size of 2 bits are more efficient in area-time product parameter than those of SDA implementations. Expand
Reducing hardware requirement in FIR filter design
A hardware optimization scheme based upon minimum-adder CSD multiplier blocks is combined with a technique for trading adders for delays to reduce hardware requirements for fixed-coefficient FIRExpand
Xilinx Spartan-II FIR Filter Solution
  • 2000