Implementation of Clock Gating Logic by Matching Factored Forms

@inproceedings{Nirosha2015ImplementationOC,
  title={Implementation of Clock Gating Logic by Matching Factored Forms},
  author={D. Nirosha and T. Thangam},
  year={2015}
}
Clock gating is one among the most widespread circuit technique to scale back power consumption. Clock gating is sometimes done at the register transfer level (RTL). Automatic synthesis of clock gating in gate level has been less explored, however it’s certainly additional convenient to designers. Clock gating consists of 2 steps: extraction of gating… CONTINUE READING