Implementation of 2D-DCT Based on FPGA with Verilog HDL

@inproceedings{Ye2011ImplementationO2,
  title={Implementation of 2D-DCT Based on FPGA with Verilog HDL},
  author={Yunqing Ye and S. Cheng},
  year={2011}
}
Discrete Cosine Transform is widely used in image compression. This paper describes the FPGA implementation of a two dimensional (8×8) point Discrete Cosine Transform (8×8 point 2D-DCT) processor with Verilog HDL for application of image processing. The row-column decomposition algorithm and pipelining are used to produce the high quality circuit design with the max clock frequency of 318MHz when implemented in a Xinlinx VIRTEX-II PRO FPGA chip. 
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