Implementation for Multiplying IEEE 754-2008 Binary 32 Bit Number Using Verilog

@article{Kumar2014ImplementationFM,
  title={Implementation for Multiplying IEEE 754-2008 Binary 32 Bit Number Using Verilog},
  author={Amit Kumar and Snehprabha Lad},
  journal={2014 International Conference on Computational Intelligence and Communication Networks},
  year={2014},
  pages={1011-1015}
}
The main aim of this paper is to design a parameterized 32 bit floating point multiplier which is based on IEEE 754-2008 binary interchange format. The proposed work is capable of checking overflow and underflow using corresponding flags by flagger circuit. In this design rounding modes are also considered based on the two bit control signal provided as input such as round to nearest even, round to zero, round to positive infinity and round to negative infinity for better accuracy of output… CONTINUE READING

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