Implementation Results of a Windowed FFT
@inproceedings{Hampson2002ImplementationRO, title={Implementation Results of a Windowed FFT}, author={Grant A. Hampson}, year={2002} }
1 Windowing FPGA Hardware Figure 1 illustrates the hardware required to implement a windowing function. The window ROM contains 1024 words, each 10-bits wide. (The ROM could be changed to RAM at a later date if the window is required to change in real-time.) The window ROM block contains an address counter which cycles through the window locations sequentially. (For symmetrical windows it could be possible to have a ROM half the length.)
3 Citations
An FPGA-based signal processing system for a 77 GHz MEMS tri-mode automotive radar
- Engineering, Business2011 22nd IEEE International Symposium on Rapid System Prototyping
- 2011
An FPGA implemented signal processing algorithm to determine the range and velocity of targets using a MEMS based tri-mode 77 GHz FMCW automotive radar has been presented and is better than the state-of the art Bosch LRR3 radar sensor.
An FPGA-based 77 GHZ MEMS radar signal processing system for automotive collision avoidance
- Engineering2011 24th Canadian Conference on Electrical and Computer Engineering(CCECE)
- 2011
An FPGA implemented signal processing algorithm to determine the range and velocity of targets using a MEMS based FMCW 77 GHz long range automotive radar has been presented. The MEMS radar uses two…
Digital Receiver For Interference Suppression in Microwave Radiometry
- Business
- 2001
Recent results are reviewed from an IIP project on the development of digital backends for microwave radiometer systems. The digital backends developed implement real-time RFI suppression algorithms…
References
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Implementation of a Single FFT Processor
- Computer Science
- 2002
This document describes a FPGA implementation and simulation of the FFT component of the IIP Radiometer RFI processor described in [1], with special emphasis on its floating point outputs.
A Possible 100 MSPS Altera FPGA FFT Processor
- Computer Science
- 2002
This document describes a FPGA implementation and simulation of the FFT component of the IIP Radiometer RFI processor described in [1], and several ideas are proposed for a 100 MSPS FFT processor.
An FPGA Implementation of the Digital IF Processor
- Computer Science
- 2002
This document describes the simulation and FPGA implementation of the IIP Radiometer Digital IF Section and the results of Matlab simulations of the structure shown in Figure 1.