An architectu?’e synthesis method for the automated design of high-performance application-specific processors has been p?’oposed. This method divides the design task into the Specification Optimization (behavioml) and Implementation Optimization (structural) phases. In an eaI’iieT pUpeT[~], poweTfui algoTiihms foI’ peI’forming specification optimization aTe pTesented. High peTfow mance is achieved via exploitation of fine-groin parallelism. The architecture design style uses a iemplate resembling a scalable VeTy Long Instruction Word (VLIW) pTocessoT. This papeT pTesents new a~goTithms foT performing implementation optimization, which map the optimized specification in the form of highly paTallelized code to eficient haTdwaTe imp~ementations. A scalable implementation template is used to constTain the implementation style. Graph coloTing algorithms aTe employed to pToduce the optimized implementations. The entire architecture synthesis pToceduTe has been implemented and applied to numeTous examples. Results on these examples are presented. Speedups in the range of ,2.6 to 7.7 oveT contemporary RISC processors have been obtained. The computation times needed foT the synthesis of these examples are on the oTder of a few seconds.
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