Implementation Of Clock Gating Logic By Matching Factored Forms

Abstract

M. Tech scholar in VLSI System Design, Department of ECE, Sri Venkatesa Perumal College of Engineering & Technology, Puttur, Chittoor (dt), A.P. Associate Professor & HOD, Department of ECE, Sri Venkatesa Perumal College of Engineering & Technology, Puttur, Chittoor (dt), A.P. kirankumari424@gmail.com, nagaraj9s@gmail.com Abstract — Clock gating is one… (More)

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