Impact of single pMOSFET dielectric degradation on NAND circuit performance

@article{Estrada2008ImpactOS,
  title={Impact of single pMOSFET dielectric degradation on NAND circuit performance},
  author={D. Estrada and M. L. Ogas and R. G. Southwick and P. M. Price and R. J. Baker and William B Knowlton},
  journal={Microelectronics and reliability},
  year={2008},
  volume={48 3},
  pages={
          354-363
        }
}
Degradation of CMOS NAND logic circuits resulting from dielectric degradation of a single pMOSFET using constant voltage stress has been examined by means of a switch matrix technique. As a result, the NAND gate rise time increases by greater than 65%, which may lead to timing errors in high frequency digital circuits. In addition, the NAND gate DC switching point voltage shifts by nearly 11% which may be of consequence for analog or mixed signal applications. Experimental results for the… CONTINUE READING

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