Impact of read enable (RE) signal duty cycle distortion (DCD) in NAND flash SI simulation

@article{Mobin2017ImpactOR,
  title={Impact of read enable (RE) signal duty cycle distortion (DCD) in NAND flash SI simulation},
  author={Sayed Mobin and Balaji Raghunathan and Arkady Katz},
  journal={2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)},
  year={2017},
  pages={1-4}
}
Impact of Read Enable (RE) signal's Duty Cycle Distortion (DCD) must be integrated in NAND to Flash Management Controller (FMC) SI simulation to predict system level performance accurately in multi-die, high performance systems. Assuming 50% duty cycle signal at the input to NAND driver is too optimistic. Both FMC and NAND contribute a portion of duty cycle distortion in the NAND read cycle. This paper identifies the gap in conventional SI simulation and describes how to reduce this gap in the… Expand
Understanding NAND AC Timing Parameters and How to Accurately Implement them in SI Simulations
Statistical Approach to Analyze Duty Cycle Jitter Amplification in NAND Flash Memory System
  • Sayed Mobin, Cindy Cui, F. Rao
  • Computer Science
  • 2018 IEEE 27th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)
  • 2018

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