Impact of local back biasing on performance in hybrid FDSOI/bulk high-k/metal gate low power (LP) technology

  title={Impact of local back biasing on performance in hybrid FDSOI/bulk high-k/metal gate low power (LP) technology},
  author={Claire Fenouillet-B{\'e}ranger and P. Perreau and Thomas Benoist and C. Richier and S{\'e}bastien Haendler and J. Pradelle and Jaime Bustos and Ph. Brun and L. Tosti and Olivier Weber and François Andrieu and Brett Orlando and D. Pellissier-Tanon and Francesco Abbate and C. Pvichard and R{\'e}mi Beneyton and M. Gregoire and J. Ducote and P. Gouraud and A. Margain and Craig Borowiak and Ricardo Bianchini and Nicolas Planes and Emmanuel Gourvest and K. K. Bourdelle and B. Y. Nguyen and T. Poiroux and Thomas Skotnicki and Olivier Faynot and Fr{\'e}d{\'e}ric Boeuf},
  journal={2012 13th International Conference on Ultimate Integration on Silicon (ULIS)},
In this paper, we study how to boost the performance of FDSOI devices with High-K and Single Metal gate by using the combination of UTBOX GP and local back biasing integrated with our hybrid process. The interest of local back biasing is highlighted in term of VT modulation and power management study on the 45 nm 0.374 μm2 bitcells and on the ESD functionality as compared to bulk technology. 

From This Paper

Figures, tables, and topics from this paper.


Publications citing this paper.
Showing 1-8 of 8 extracted citations

The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks

2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS) • 2018

Extending HKMG scaling on CMOS with FDSOI: Advantages and integration challenges

2016 International Conference on IC Design and Technology (ICICDT) • 2016

Predictive effective mobility model for FDSOI transistors using technology parameters

2016 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) • 2016
View 1 Excerpt

Laser attacks on integrated circuits: From CMOS to FD-SOI

2014 9th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) • 2014

Lower DIBL in inverted substrate of UTBB SOI n-MOSFETs

2014 IEEE International Conference on Semiconductor Electronics (ICSE2014) • 2014


Publications referenced by this paper.

Aknowledgement: This work was partially supported by the European Project DECISIF. Fig.18: Schematic representation of a gated diode at high injection level: a- FDSOI; b- bulk

C. Fenouillet-Beranger
VLSI • 2010
View 2 Excerpts

Similar Papers

Loading similar papers…