Impact of local back biasing on performance in hybrid FDSOI/bulk high-k/metal gate low power (LP) technology

@article{FenouilletBranger2012ImpactOL,
  title={Impact of local back biasing on performance in hybrid FDSOI/bulk high-k/metal gate low power (LP) technology},
  author={Claire Fenouillet-B{\'e}ranger and P. Perreau and Thomas Benoist and C. Richier and S{\'e}bastien Haendler and J. Pradelle and Jaime Bustos and Ph. Brun and L. Tosti and Olivier Weber and François Andrieu and Brett Orlando and D. Pellissier-Tanon and Francesco Abbate and C. Pvichard and R{\'e}mi Beneyton and M. Gregoire and J. Ducote and P. Gouraud and A. Margain and Craig Borowiak and Ricardo Bianchini and Nicolas Planes and Emmanuel Gourvest and K. K. Bourdelle and B. Y. Nguyen and T. Poiroux and Thomas Skotnicki and Olivier Faynot and Fr{\'e}d{\'e}ric Boeuf},
  journal={2012 13th International Conference on Ultimate Integration on Silicon (ULIS)},
  year={2012},
  pages={165-168}
}
In this paper, we study how to boost the performance of FDSOI devices with High-K and Single Metal gate by using the combination of UTBOX GP and local back biasing integrated with our hybrid process. The interest of local back biasing is highlighted in term of VT modulation and power management study on the 45 nm 0.374 μm2 bitcells and on the ESD functionality as compared to bulk technology. 

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Aknowledgement: This work was partially supported by the European Project DECISIF. Fig.18: Schematic representation of a gated diode at high injection level: a- FDSOI; b- bulk

C. Fenouillet-Beranger
VLSI • 2010
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