Impact of gate oxide breakdown in logic gates from 28nm FDSOI CMOS technology

Abstract

For advanced CMOS nodes, high performance is reached with the down scaling of both critical gate length and dielectrics stack. The aggressive reduction of dielectric thickness leads to a reduction of reliability margin due to breakdown. However, the first breakdown (BD) event does not always cause a functional failure in digital circuits. Lifetime extension… (More)
DOI: 10.1109/IRPS.2015.7112782

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