Impact of data serialization over TSVs on routing congestion in 3D-stacked multi-core processors


3D integration can alleviate routing congestion, reducing the wirelength and improving performances. Nevertheless, each TSV still occupies non-negligible silicon area: as the number of TSV increases, their effect on the chip routing is detrimental. The reduction in the number of 3D vias obtained with the adoption of serial vertical connections can relieve… (More)
DOI: 10.1016/j.mejo.2015.12.004


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