Impact of Write Pulse and Process Variation on 22 nm FinFET-Based STT-RAM Design: A Device-Architecture Co-Optimization Approach

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@article{Xu2015ImpactOW, title={Impact of Write Pulse and Process Variation on 22 nm FinFET-Based STT-RAM Design: A Device-Architecture Co-Optimization Approach}, author={Cong Xu and Yang Zheng and Dimin Niu and Xiaochun Zhu and Seung H. Kang and Yuan Xie}, journal={IEEE Trans. Multi-Scale Computing Systems}, year={2015}, volume={1}, pages={195-206} }