Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS

  title={Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS},
  author={Vikas Chandra and Robert C. Aitken},
  journal={2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems},
  • V. Chandra, R. Aitken
  • Published 2008
  • Computer Science
  • 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems
With each technology node shrink, a silicon chip becomes more susceptible to soft errors. The susceptibility further increases as the voltage is scaled down to save energy. Based on analysis on cells from commercial libraries, we have quantified the increase in the soft error probability across 65 nm and 45 nm technology nodes at different supply voltages using the Qcrit based simulation methodology. The Qcrit for both bit cells and latches decreases by ~30% as the designs are scaled from 65 nm… Expand
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