Impact of Technology Scaling on Metastability Performance of CMOS Synchronizing Latches

@inproceedings{Baghini2002ImpactOT,
  title={Impact of Technology Scaling on Metastability Performance of CMOS Synchronizing Latches},
  author={Maryam Shojaei Baghini and Madhav P. Desai},
  booktitle={VLSI Design},
  year={2002}
}
In this paper, we use circuit simulations to characterize the effects of technology scaling on the metastability parameters of CMOS latches used as synchronizers. We perform this characterization by obtaining a synchronization error probability curve from a histogram of the latch delay. The main metastability parameters of CMOS latches are Tm and Tw. Tm is the exponential time constant of the rate of decay of metastability and Tw is effective size of metastability window at a normal propagation… CONTINUE READING
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