Impact of Scaling on Analog Performance and Associated Modeling Needs

  title={Impact of Scaling on Analog Performance and Associated Modeling Needs},
  author={Boris Murmann and Parastoo Nikaeen and D. J. Connelly and R G Dutton},
  journal={IEEE Transactions on Electron Devices},
This paper explores modeling and technology-scaling issues related to analog performance in advanced CMOS technologies. Performance metrics for analog circuits are defined, to provide insight into the impact of device scaling on power-constrained analog circuit design. Current and previous generation technologies (90 nm and older) are evaluated using standard compact models. Technology nodes below 90 nm are simulated at the device level to show trends in analog performance metrics and to… CONTINUE READING
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