• Corpus ID: 41181961

Impact of Multi-Trap Assisted Tunneling on Gate Leakage of CMOS Memory Devices

@inproceedings{Entner2005ImpactOM,
  title={Impact of Multi-Trap Assisted Tunneling on Gate Leakage of CMOS Memory Devices},
  author={Robert Entner and Andreas Gehring and Hans Kosina and Tibor Grasser and Siegfried Selberherr and Christian Doppler},
  year={2005}
}

• R. Entner, A. Gehring, +3 authors C. Doppler
• Published 8 May 2005
• Engineering

Dielectrics of state-of-the-art memory cells subject to repeated high fleld stress can have a high defect density. Thus, not only direct tunneling but also trap-assisted tunneling plays an important role. In this work a new approach for modeling gate leakage currents through highly degraded dielectrics is proposed. By rigorous simulation we show that multi-trap assisted tunneling becomes important for highly degrad dielectrics with thicknesses above approximately 4 nm, there it exceeds the single-trap assisted and direct tunneling components.