Impact of Mechanical Stress on the Full Chip Timing for Through-Silicon-Via-based 3-D ICs

Abstract

In this paper, we study the impact of through-silicon-via (TSV) and shallow trench isolation (STI) stress on the timing variations of 3-D IC. We also propose the first systematic TSV-STI-stress-aware timing analysis and show how to optimize layouts for better performance. First, we generate a stress contour map with an analytical radial stress model for TSV… (More)
DOI: 10.1109/TCAD.2013.2237770

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Cite this paper

@article{Athikulwongse2013ImpactOM, title={Impact of Mechanical Stress on the Full Chip Timing for Through-Silicon-Via-based 3-D ICs}, author={Krit Athikulwongse and Jae-Seok Yang and David Z. Pan and Sung Kyu Lim}, journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, year={2013}, volume={32}, pages={905-917} }