Impact of FPGA architecture on resource sharing in high-level synthesis

@inproceedings{Hadjis2012ImpactOF,
  title={Impact of FPGA architecture on resource sharing in high-level synthesis},
  author={Stefan Hadjis and Andrew Canis and J. Anderson and Jongsok Choi and Kevin Nam and S. Brown and T. Czajkowski},
  booktitle={FPGA '12},
  year={2012}
}
  • Stefan Hadjis, Andrew Canis, +4 authors T. Czajkowski
  • Published in FPGA '12 2012
  • Computer Science
  • Resource sharing is a key area-reduction approach in high-level synthesis (HLS) in which a single hardware functional unit is used to implement multiple operations in the high-level circuit specification. We show that the utility of sharing depends on the underlying FPGA logic element architecture and that different sharing trade-offs exist when 4-LUTs vs. 6-LUTs are used. We further show that certain multi-operator patterns occur multiple times in programs, creating additional opportunities… CONTINUE READING
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