Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems

@article{Choi2012ImpactOC,
  title={Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems},
  author={Jongsok Choi and Kevin Nam and Andrew Canis and J. Anderson and S. Brown and T. Czajkowski},
  journal={2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines},
  year={2012},
  pages={17-24}
}
  • Jongsok Choi, Kevin Nam, +3 authors T. Czajkowski
  • Published 2012
  • Computer Science
  • 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines
  • We describe new multi-ported cache designs suitable for use in FPGA-based processor/parallel-accelerator systems, and evaluate their impact on application performance and area. The baseline system comprises a MIPS soft processor and custom hardware accelerators with a shared memory architecture: on-FPGA L1 cache backed by off-chip DDR2 SDRAM. Within this general system model, we evaluate traditional cache design parameters (cache size, line size, associativity). In the parallel accelerator… CONTINUE READING
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